AMD RDNA3 Instruction Set Architecture Reference Guide

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We're pleased to announce the availability of the AMD RDNA™ 3 ISA reference guide, following the release of our first RDNA 3-based GPU products. The ISA guide is most useful for anyone interested in the lowest level operation of the RDNA 3 shader core, be that shader compiler writers, tools authors, and any game or application developer that needs to optimize their shaders for the new GPU.

The guide covers the whole shader core execution model, including program state, the various wave execution models, how the shader core interacts with the memory hierarchy, the available instructions including their encodings, and lots more.

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This document describes the current environment, organization and program state of AMD "RDNA3" Generation devices. It details the instruction set and the microcode formats native to this family of processors that are accessible to programmers and compilers.

The document specifies the instructions (include the format of each type of instruction) and the relevant program state (including how the program state interacts with the instructions). Some instruction fields are mutually dependent; not all possible settings for all fields are legal. This document specifies the valid combinations.

The main purposes of this document are to:
1. Specify the language constructs and behavior, including the organization of each type of instruction in both text syntax and binary format
2. Provide a reference of instruction operation that compiler writers can use to maximize performance of the processor

This document is intended for programmers writing application and system software, including operating
systems, compilers, loaders, linkers, device drivers, and system utilities. It assumes that programmers are writing compute-intensive parallel applications (streaming applications) and assumes an understanding of requisite programming practices.

Links:
- Announcement
- AMD RDNA3 ISA reference guide (606-page PDF)