0 Members and 1 Guest are viewing this topic.
With an estimated die-area of 430 mm² (18% bigger than "Tahiti,") the chip physically features 2,816 stream processors (SPs) spread across 44 clusters with 64 SPs each (a 37.5% increase over "Tahiti"). The chip features four independent raster engines, compared to two independent ones on "Tahiti." This could translate into double the geometry processing muscle as "Tahiti," with four independent tessellation units. The memory interface of the chip is expected to be 384-bit wide, based on the GDDR5 specification. Given the way TMUs are arranged on chips based on this architecture, one can deduce 176 TMUs on the chip. The ROP count could be 32 or 48. The chip will feature hardware support for DirectX 11.2, including the much hyped shared resources (mega-texture) feature.