Author Topic: AMD Graphics Cores Next (GCN) Architecture  (Read 3040 times)

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Stefan

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AMD Graphics Cores Next (GCN) Architecture
« on: June 30, 2012, 12:55:21 PM »
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Over the last 15 years, graphics processors have continually evolved and are on the cusp of becoming an integral part of the computing landscape.   
The first designs employed special purpose hardware with little flexibility. Later designs introduced limited programmability through shader programs,  and eventually became highly programmable throughput computing devices that still maintained many graphics-specific capabilities.

The performance and efficiency potential of GPUs is incredible. Games provide visual quality comparable to leading films, and early adopters in the scientific community have seen an order of magnitude improvement in performance, with high-end GPUs capable of exceeding 4 TFLOPS (Floating point Operations per Second). The power efficiency is remarkable as well; for example, the AMD Radeon™ HD 7770M GPU achieves over 1 TFLOPS with a maximum power draw of 45W.

Key industry standards, such as OpenCL™, DirectCompute and C++ AMP recently have made GPUs accessible to programmers. The challenge going forward is creating seamless heterogeneous computing solutions for mainstream applications. This entails enhancing performance and power efficiency, but also  programmability and flexibility. Mainstream applications demand industry standards that are adapted to the modern ecosystem with both CPUs and GPUs  and a wide range of form factors from tablets to supercomputers. 

AMD’s Graphics Core Next (GCN) represents a fundamental shift for GPU hardware and is the architecture for future programmable and heterogeneous  systems. GCN is carefully optimized for power and area efficiency at the 28nm node and will scale to future process technologies in the coming years.   
The heart of GCN is the new Compute Unit (CU) design that is used in the shader array, which is described in detail in the following sections.

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